1. Field of the Invention
The present invention relates generally to a load generator and a semiconductor memory device using the load generator, and in particular to the control of voltage swings in logic signals transmitted to a pair of complementary signal lines.
2. Description of the Related Art
One way to increase the speed of a semiconductor memory device is to increase the rate which data is read from the memory device. Past attempts at increasing data read rates have focused on reducing the voltage swing in complimentary logic signals transmitted on a pair of data buses (i.e., on a complementary signal line pair). This shortens the time necessary to invert the complementary signals, in effect, increasing data read rates. One type of conventional semiconductor memory device accomplishes this by using a load generator.
FIG. 1 schematically illustrates a typical circuit arrangement for a random access memory (RAM) device. The circuit includes a memory cell array 50 formed from two-dimensionally arranged memory cells (not shown). Each of these memory cells stores 1 bit of data. As is well known in this field, the data reading and/or writing operations are carried out with respect to selected memory cells. The sense amplifier 51, coupled to the memory cell array 50, amplifies data read from the selected memory cells on bit lines (not shown). The sense amplifier 51 couples to a sense buffer 52 via a pair of data buses DB and /DB. A load generator 54 is connected in parallel along data buses DB and /DB, between the sense amplifier 51 and sense buffer 52. The data buses DB and /DB transfer the data read from the memory cells to the sense buffer 52.
The potentials of data buses DB and /DB reflect the potential the data read from the memory cells. For example, when the data read from the memory cell corresponds to "0", the potential of the data bus DB goes low and the potential of the data bus /DB goes high. Conversely, when the data read from the memory cell corresponds to "1", the potential of the data bus DB goes high, and the potential of the data bus /DB goes low. As described above, the read data read from the memory cells is output as the complementary signals appearing on the pair of data buses DB and /DB. The sense buffer 52 and the output buffer 53 produce the output data "D.sub.out " in response to the complementary signals.
The load generator 54 reduces the potential difference between the complementary signals appearing on the pair of data buses DB and /DB. In effect, the load generator 54 reduces the voltage swing of the complementary logic signals, shortening the time required to invert the level of the signals on the data buses DB and /DB.
In particular, when the voltage level of the data read from the selected memory cell is "0" the potential at the data bus DB is set low (e.g., to 0 volt) and the potential at the data bus /DB is set high (e.g., to 5 volts). If data, contained in the next cell read, is "1", the voltage potential on data bus DB has to be inverted low to high, while the voltage potential on the data bus /DB has to be inverted high to low. During the inversion process, neither the sense buffer 52 nor the output buffer 53 outputs data D.sub.out. Accordingly, the larger the logic voltage swing of the complementary signals, the longer the time needed to invert later occurring complementary signals. Consequently, it is desirable to reduce the potential level difference in the complementary data bus signals by using the load generator 54 in order to achieve higher memory device speeds.
FIG. 2 roughly shows the circuit arrangement of the load generator 54 which has been proposed by Chul M. Jung et al., of SAMSUNG ELECTRONICS Company, in Symposium On VLSI Circuits held in 1993. The load generator 54 is composed of six enhancement type P-channel MOS transistors 61 to 66. The first to third PMOS transistors 61 to 63 are connected in series between the high potential power supply Vcc and the low potential power supply Vss. Similarly, the fourth to sixth PMOS transistors 64 to 66 are connected in series between the high potential power supply Vcc and the low potential power supply Vss.
The first and fourth PMOS transistors 61 and 64 each has its source connected to the high potential power supply Vcc and its gate connected to the low potential power supply Vss. As a result, the PMOS transistors 61 and 64 are continuously turned ON.
The third and sixth PMOS transistors 63 and 66 each has its drain connected to the low potential power supply Vss and its gate available to receive a control signal CS. The control signal CS is a chip select signal capable of enabling or disabling the RAM. When the control signal CS is set high, the RAM is disabled. Conversely, when the control signal CS is set low, the RAM is enabled. When the control signal CS is set low, the PMOS transistors 63 and 66 are turned ON, activating the load generator 54.
The second PMOS transistor 62 has its source connected to the drain of the first transistor 61, its drain connected to the source of the third transistor 63, and its gate connected to the drain of the fifth transistor 65. The fifth PMOS transistor 65 has its source connected to the drain of the fourth transistor 64, its drain connected to the source of the sixth transistor 66, and its gate connected to the drain of the second transistor 62. The data bus DB is connected to the node N1 between the first transistor 61 and the second transistor 62. The data bus /DB is connected to the node N2 between the fourth transistor 64 and the fifth transistor 65.
When the low-level control signal CS is input to the gates of the third and sixth transistors 63 and 66, all of the transistors 61 to 66 are activated ON. The potentials then at these nodes N1 and N2 are divided by the resistance values of the respective transistors 61 to 66 when activated. In particular, the divided voltage amounts depend on the relationship of channel widths W61 to W66 of the respective transistors 61 to 66. In the load generator shown in FIG. 2, the channel widths W61 to W66 are, for example, designed to satisfy the relationship: EQU W61 : W62 : W63=W64 : W65 : W66=1 : 1 : 2.
The potentials at the nodes N1 and N2 are set to the potentials corresponding to the potential at which the sense amplifier 51 is most sensitive to the signals on the data buses.
Although the potential levels of the data buses DB and /DB are initially set approximately midway between high and low voltage potentials, the potential on the data bus changes in synchronism with the data read from the memory cell. When, for instance, the data of "1" is read, the potential at the data bus DB goes high and the potential at the data bus /DB goes low. Consequently, the current I62 flowing through the second transistor 62 increases, while the current I65 flowing through the fifth transistor 65 decreases. Accordingly, the drain voltage of the second transistor 62 is applied to the gate of the fifth transistor 65 and the drain voltage of the fifth transistor 65 is applied to the gate of the second transistor 62. As a result, the currents I62 and I65, initially set equal to each other, increase and decrease respectively, and remain constant thereafter. This produces the difference current ".DELTA.I" between the increased current I62 and the decreased current I65. Accordingly, the potential at the node N1 increases and the potential at node N2 decreases due to the differential current .DELTA.I. The new potential levels at nodes N1 and N2, i.e., the potential levels at the data buses DB and /DB, are maintained by the transistors 62 and 65.
Thereafter, if data representative of "0" is read from the memory cell, the potential levels on the data buses DB and /DB must be inverted. In particular, the potential at the data bus DB must be set to the potential lower than its initial potential by the voltage difference caused by the differential current .DELTA.I, whereas the potential at the data bus /DB must be set to the potential higher than its initial potential by the voltage difference caused by the differential current .DELTA.I.
One challenge involving the design of memory devices is that the output data D.sub.out from the RAM must often be supplied to semiconductor devices operating at different voltage potentials from that of the RAM. For example, the other devices could have a CMOS level specification corresponding to the logic voltage swing of 0 volt to 5 volts, or a TTL level specification corresponding to the logic voltage swing of 0.8 volts to 2.2 volts. In such a case, either the output signal from the RAM would have to be amplified, or the level of the output signal would have to be converted for its potential to correspond to that required by the other semiconductor devices.
However, it is difficult to amplify or convert the levels of signals which exhibit small voltage swings. Consequently, it is difficult to amplify or convert the complementary signals on the data buses DB and /DB. Thus, even when the difference between the potential levels at the data buses DB and /DB is reduced by employing the load generator 54, ostensively to shorten the time period required to invert the signals, the data reading operations will exhibit no increased speed if the output data D.sub.out must be amplified or its level converted.